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The MYC-C7Z015 CPU Module is an SOM (System on Module) board based
on Xilinx XC7Z015 (Z-7015) All Programmable
System-on-Chip (SoC) which is among the Xilinx
Zynq-7000 family, featuring integrated dual-core ARM
Cortex-A9 processor with Xilinx 7-series FPGA logic, four 6.25Gbps SerDes transceivers and one
PCIe Gen2 x 4 integrated block. The MYC-C7Z015 module has 1GB DDR3 SDRAM, 4GB eMMC, 32MB quad SPI Flash, a Gigabit Ethernet PHY, a USB
PHY and external watchdog on board. It provides a large number of I/O signals for ARM peripherals and FPGA
I/Os through two 0.8mm pitch 140-pin board-to-board connectors, which is ideal for your next embedded
design.
MYC-C7Z015 CPU Module
The MYC-C7Z015 CPU Module is compatible
with MYIR’s MYC-C7Z010/20 CPU Modules and they can share the same base board which
is designed by MYIR for evaluation or prototype purpose. The MYD-C7Z015
development board takes full features of the Zynq-7015 SoC. It has full
features of the MYD-C7Z010/20 development board, additionally, it has one PCIe
interface with two lanes and one SFP transceiver module interface.
MYD-C7Z015 Development Board
The MYC-C7Z015 CPU Module is ready to run Linux 5.4.0. It can be used in a variety of commercial, medical, automation, industrial, and military embedded applications.
Features
Mechanical Parameters
-
Dimensions: 75mm x 55mm (12-layer PCB design)
-
Power supply: 5V/0.5A
-
Working temp.: -40~85 Celsius (industrial
grade)
SoC
-
Xilinx XC7Z015-2CLG485 (Zynq-7015)
- 766MHz ARM® dual-core Cortex™-A9 MPCore processor (up to 866MHz)
- Integrated Artix-7 class FPGA subsystem with 74K logic cells, 46,200
LUTs, 160 DSP slices
- NEON™ & Single / Double Precision Floating Point for each processor
- Supports a Variety of Static and Dynamic Memory Interfaces
- Four high-speed SerDes transceivers up to 6.25Gbps
- Four PCIe Gen2 hardened, integrated IP blocks
Memory
-
1GB DDR3 SDRAM (512MB*2)
-
4GB eMMC
-
32MB QSPI Flash (16MB is optional)
Peripherals and Signals Routed to Pins ( MYC-C7Z015 pin-out description)
-
10/100/1000M Ethernet PHY
-
USB PHY
-
External watchdog
-
Three LEDs
- One blue LED for power indicator
- One red LED for FPGA program done indicator
- One green user LED
-
Two 0.8mm pitch 140-pin board-to-board expansion connectors bring out below signals:
- One Gigabit Ethernet
- One USB OTG 2.0
- Up to two Serial ports (reused from PS_MIO, can also
be implemented through PL pins)
- Up to two I2C (reused from PS_MIO, can also be implemented through PL pins)
- Up to two CAN BUS (reused from PS_MIO, can also be implemented through PL
pins)
- One SPI (reused from PS_MIO, can also be implemented through PL pins)
- ADC (one independent differential ADC, 16-channel ADC brought out through PL
pins)
- One SDIO (PS SDIO 0)
- Bank 13 (PL I/O configurable as up to 18 LVDS pairs and 1 single-ended I/O or
37 single-ended I/O)
- Bank 34 (PL I/O configurable as up to 24 LVDS pairs and 2 single-ended I/O or
50 single-ended I/O)
- Bank 35 (PL I/O configurable as up to 24 LVDS pairs and 2 single-ended I/O or
50 single-ended I/O)
- Bank 112 (4 GTP serial transceivers, 2 reference clock input)
OS Support
Other MYIR's Xilinx Products
http://www.myirtech.com/xilinxseries.asp
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Z-turn Board V2 Single Board Computer (based on Zynq-7010 / 7020)
MYD-C7Z010/20-V2 Development Board (MYC-C7Z010/20-V2 CPU Module as core board)
MYD-Y7Z010/20-V2 Development Board (MYC-Y7Z010/20-V2 CPU Module as core board)
MYD-CZU3EG/4EV/5EV-V2 Development Board (MYC-CZU3EG/4EG/5EV-V2 CPU Module as core board)
FZ5 Card (AI Accelerator Card based on Zynq UltraScale+ ZU5EV MPSoC)
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Overview
