Xilinx SDSoC Development Environment

The Xilinx SDSoC™ development environment is a member of the Xilinx SDx™ family that provides a greatly simplified ASSP-like
C/C++ programming experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® All Programmable SoC and MPSoC deployment. Complete with the industry’s first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming.

To access the capabilities of SDSoC, please visit http://www.xilinx.com/products/design-tools/software-zone/sdsoc.html
MYIR Tech Limited is an SDSoC development environment-qualified Xilinx Alliance Member and offers Single Board Computers, Development Boards, CPU Modules and Design services based on Xilinx Zynq-based SoCs. At present, we have made our Z-turn Board (with XC7Z020-1CLG400C) and MYD-C7Z020 development board to support using the SDSoC™ development environment. In future, more and more of MYIR's other Xilinx products will be able to support the SDSoC also.
Z-Turn_7020_SDSoc_Platform (2.15MB)
MYD-C7Z020_SDSoc_Platform (1.57MB)
MYIR is a Xilinx Alliance Member, welcome to use MYIR's Xilinx products!
We also offer custom design services, welcome your inquiry!
http://www.xilinx.com/alliance/memberlocator/1-2wv1bc.html

Z-turn Board
Item
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Features
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SoC
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Xilinx XC7Z010-1CLG400C (Zynq-7010) or XC7Z020-1CLG400C (Zynq-7020)
- 667MHz ARM® dual-core Cortex™-A9 MPCore processor (up to 866MHz)
- Integrated Artix-7 class FPGA subsystem
with 28K logic cells, 17,600 LUTs, 80 DSP slices (for XC7Z010)
with 85K logic cells, 53,200 LUTs, 220 DSP slices (for XC7Z020)
- NEON™ & Single / Double Precision Floating Point for each processor
- Supports a Variety of Static and Dynamic Memory Interfaces
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Memory
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1GB DDR3 SDRAM (2 x 512MB, 32-bit)
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Storage
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16MB QSPI Flash
TF card interface
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Communications
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1 x 10/100/1000M Ethernet
1 x CAN
1 x Mini USB2.0 OTG
1 x USB-UART debug interface
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Display
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1 x HDMI (supports 1080p resolution)
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User I/O
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Brought out via two 1.27mm pitch 80-pin SMT female connectors
- 90/106 user I/O (7010/7020)
- Configurable as up to 39 LVDS pairs I/O
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Dimensions
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63mm x 102mm x 1.6mm (8-layer PCB design)
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Power supply
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USB power supply or DC 5V/2A
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Others
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Onboard three-axis acceleration sensor and temperature sensor
1 x 2.54mm pitch 14-pin JTAG interface
2 x Buttons (1x Reset, 1 x User)
4-channel toggle switch
5 x LEDs (3 x User LEDs, 1 x Power indicator, 1 RGB LED)
1 x Buzzer
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OS support
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Linux 3.15.0
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Target Applications
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Evaluation and Prototyping for Zynq-7000 AP SoC
Industrial Automation
Test & measurement
Medical Equipment
Intelligent Video Surveillance
Aerospace and military
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MYD-C7Z010/20 Development Board

MYD-C7Z010/20 Development Board
Mechanical Parameters
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Dimensions: 190mm x 110mm (base board), 75mm x 55mm (CPU Module)
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PCB layers: 4-layer design (base board), 10-layer design (CPU Module)
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Power supply: 12V/0.5A (base board), 5V/0.5A (CPU Module)
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Working temp.: 0~70 Celsius
OS Support
The MYD-C7Z010/20 Controller Board (MYC-C7Z010/20 CPU Module)
MYC-C7Z010/20 Top-view MYC-C7Z010/20 Bottom-view
SoC
-
Xilinx XC7Z010-1CLG400C (Zynq-7010) or XC7Z020-1CLG400C (Zynq-7020)
- 667MHz ARM® dual-core Cortex™-A9 MPCore processor (up to 866MHz)
- Integrated Artix-7 class FPGA subsystem
with 28K logic cells, 17,600 LUTs, 80 DSP slices (for XC7Z010)
with 85K logic cells, 53,200 LUTs, 220 DSP slices (for XC7Z020)
- NEON™ & Single / Double Precision Floating Point for each processor
- Supports a Variety of Static and Dynamic Memory Interfaces
Memory
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1GB DDR3
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4GB eMMC
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32MB QSPI Flash (16MB is optional)
Peripherals and Signals Routed to Pins
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10/100/1000M Ethernet PHY
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External watchdog
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Three LEDs
- One blue LED for power indicator
- One red LED for FPGA program done indicator
- One green user LED
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Two 0.8mm pitch 140-pin board-to-board expansion connectors bring out below signals:
- One Gigabit Ethernet
- One USB OTG 2.0
- Two Serial ports
- Two I2C
- Two CAN BUS
* Serial ports, I2C and CAN signals will be reused in PS part, or implemented through PL pins
- Two SPI (can be implemented through PL pins)
- ADC (one independent differential ADC, 16-channel ADC brought out through PL pins)
- One SDIO
The MYD-C7Z010/20 Base Board (MYB-C7Z010/20)
PS Unit
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Four USB 2.0 Host ports (through USB Hub)
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One RS232 (DB9 port)
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One TF card slot (bootable)
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One CAN interface
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One 10/100/1000M Ethernet
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One 2.54mm pitch 14-pin JTAG interface (PS, PL reused)
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Battery backed RTC
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One User Button (One I2C, can be connected to LCD and Resistive Touch Screen)
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Jumpers
- One for booting selection from TF card or QSPI
- One for JTAG selection for using PS and PL reused or independent JTAG configured through PL pins
- One for selection if adding FMC module to JTAG
PL Unit
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One XADC interface
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One Xilinx standard LPFMC interface
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One HDMI interface (16-bit YCrCb, support 1080p display, do not support audio)
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LCD/Touch screen interface (16-bit RGB, signals reused with HDMI, supports resistive and capacitive touch screen)
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Two LEDs (one for FMC module detection, one for power indicator)
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Three-channel PMoD (only for XC7Z020)
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